View AD8034ARTZ-REEL_8231479.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low cost, 80 mhz fastfet op amps ad8033/ad8034 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2008 analog devices, inc. all rights reserved. features fet input amplifier 1 pa typical input bias current very low cost high speed 80 mhz, ?3 db bandwidth (g = +1) 80 v/s slew rate (g = +2) low noise 11 nv/hz (f = 100 khz) 0.7 fa/hz (f = 100 khz) wide supply voltage range: 5 v to 24 v low offset voltage: 1 mv typical single-supply and rail-to-rail output high common-mode rejection ratio: ?100 db low power: 3.3 ma/amplifier typical supply current no phase reversal small packaging: 8-lead soic, 8-lead sot-23, and 5-lead sc70 applications instrumentation filters level shifting buffering general description the ad8033/ad8034 fast fet? amplifiers are voltage feedback amplifiers with fet inputs, offering ease of use and excellent performance. the ad8033 is a single amplifier and the ad8034 is a dual amplifier. the ad8033/ad8034 fast fet op amps in analog devices, inc., proprietary xfcb process offer significant performance improvements over other low cost fet amps, such as low noise (11 nv/hz and 0.7 fa/hz) and high speed (80 mhz bandwidth and 80 v/s slew rate). with a wide supply voltage range from 5 v to 24 v and fully operational on a single supply, the ad8033/ad8034 amplifiers work in more applications than similarly priced fet input amplifiers. in addition, the ad8033/ad8034 have rail-to-rail outputs for added versatility. despite their low cost, the amplifiers provide excellent overall performance. they offer a high common-mode rejection of ?100 db, low input offset voltage of 2 mv maximum, and low noise of 11 nv/hz. connection diagrams nc 1 ?in 2 +in 3 ?v s 4 nc 8 +v s 7 v out 6 nc 5 nc = no connect 02924-001 ad8033 v out 1 +in 3 ?v s 2 +v s 5 ?in 4 0 2924-002 ad8033 figure 1. 8-lead soic (r) figure 2. 5-lead sc70 (ks) v out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 v out2 7 ?in2 6 +in2 5 02924-003 ad8034 figure 3. 8-lead soic (r) and 8-lead sot-23 (rj) 100 0.1 1 frequency (mhz) 21 18 ?9 15 12 9 6 3 0 ?3 ?6 24 gain (db) g = +5 1000 g = +1 v out = 200mv p-p g = +10 g = +2 g = ?1 02924-004 10 figure 4. small signal frequency response the ad8033/ad8034 amplifiers only draw 3.3 ma/amplifier of quiescent current while having the capability of delivering up to 40 ma of load current. the ad8033 is available in a small package 8-lead soic and a small package 5-lead sc70. the ad8034 is also available in a small package 8-lead soic and a small package 8-lead sot-23. they are rated to work over the industrial temperature range of ?40c to +85c without a premium over commercial grade products.
important links for the ad8033_8034 * last content update 08/19/2013 12:56 am documentation an-649: using the analog devices active filter design tool an-581: biasing and decoupling op amps in single supply applications an-402: replacing output clamping op amps with input clamping amps an-417: fast rail-to-rail operational amplifiers ease design constraints in low voltage high speed systems mt-060: choosing between voltage feedback and current feedback op amps mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters mt-058: effects of feedback capacitance on vfb and cfb op amps mt-056: high speed voltage feedback op amps mt-053: op amp distortion: hd, thd, thd + n, imd, sfdr, mtpr mt-052: op amp noise figure: dont be mislead mt-050: op amp total output noise calculations for second-order system mt-049: op amp total output noise calculations for single-pole system mt-048: op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth mt-047: op amp noise mt-033: voltage feedback op amp gain and bandwidth mt-032: ideal voltage feedback (vfb) op amp a stress-free method for choosing high-speed op amps for the ad8033 an-357: operational integrators ug-112: universal evaluation board for single, high speed op amps offered in sc-70 packages ug-101: evaluation board user guide for the ad8034 an-108: jfet-input amps are unrivaled for speed and accuracy an-356: users guide to applying and measuring operational amplifier specifications ug-019: universal evaluation board for dual, high speed op amps offered in 8-lead sot-23 packages ug-128: universal evaluation board for dual high speed op amps in soic packages evaluation kits & symbols & footprints view the evaluation boards and kits page for the ad8033 view the evaluation boards and kits page for the ad8034 symbols and footprints for the ad8033 symbols and footprints for the ad8034 parametric selection tables find similar products by operating parameters high speed amplifiers selection table design tools, models, drivers & software dbm/dbu/dbv calculator analog filter wizard 2.0 power dissipation vs die temp adisimopamp? opamp stability ad8033 spice macro-model ad8034 spice macro-model photodiode preamp error budget tutorial for the ad8034 design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8033 ad8034 find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad8033/ad8034 rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? connection diagrams ...................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? maximum power dissipation ..................................................... 6 ? output short circuit .................................................................... 6 ? esd caution .................................................................................. 6 ? typical performance characteristics ............................................. 7 ? test circuits ..................................................................................... 14 ? theory of operation ...................................................................... 16 ? output stage drive and capacitive load drive ..................... 16 ? input overdrive .......................................................................... 16 ? input impedance ........................................................................ 16 ? thermal considerations ............................................................ 16 ? layout, grounding, and bypassing considerations .................. 18 ? bypassing ..................................................................................... 18 ? grounding ................................................................................... 18 ? leakage currents ........................................................................ 18 ? input capacitance ...................................................................... 18 ? applications information .............................................................. 19 ? high speed peak detector ........................................................ 19 ? active filters ............................................................................... 20 ? wideband photodiode preamp ................................................ 21 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 24 ? revision history 9/08rev. c to rev. d deleted usable input range parameter, table 1 ........................... 3 deleted usable input range parameter, table 2 ........................... 4 deleted usable input range parameter, table 3 ........................... 5 4/08rev. b to rev. c changes to format ............................................................. universal changes to features and general description ............................. 1 changes to figure 13 caption and figure 14 caption ................ 8 changes to figure 22 and figure 23 ............................................... 9 changes to figure 25 and figure 28 ............................................. 10 changes to input capacitance section ........................................ 18 changes to active filters section ................................................. 21 changes to outline dimensions ................................................... 23 changes to ordering guide .......................................................... 24 2/03rev. a to rev. b changes to features .......................................................................... 1 changes to connection diagrams ................................................. 1 changes to specifications ................................................................ 2 changes to absolute maximum ratings ....................................... 4 replaced tpc 31............................................................................. 11 changes to tpc 35 ......................................................................... 11 changes to test circuit 3 ............................................................... 12 updated outline dimensions ....................................................... 19 8/02rev. 0 to rev. a added ad8033 ................................................................... universal v out = 2 v p-p deleted from default conditions ......... universal added soic-8 (r) and sc70 (ks) .................................................. 1 edits to general description section ............................................. 1 changes to specifications ................................................................. 2 new figure 2 ...................................................................................... 5 edits to maximum power dissipation section .............................. 5 changes to ordering guide ............................................................. 5 change to tpc 3 ............................................................................... 6 change to tpc 6 ............................................................................... 6 change to tpc 9 ............................................................................... 7 new tpc 16 ....................................................................................... 8 new tpc 17 ....................................................................................... 8 new tpc 31 .................................................................................... 11 new tpc 35 .................................................................................... 11 new test circuit 9 .......................................................................... 13 sc70 (ks) package added ............................................................ 19
ad8033/ad8034 rev. d | page 3 of 24 specifications t a = 25c, v s = 5 v, r l = 1 k, gain = +2, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v out = 0.2 v p-p 65 80 mhz g = +2, v out = 0.2 v p-p 30 mhz g = +2, v out = 2 v p-p 21 mhz input overdrive recovery time ?6 v to +6 v input 135 ns output overdrive recovery time ?3 v to +3 v input, g = +2 135 ns slew rate (25% to 75%) g = +2, v out = 4 v step 55 80 v/s settling time to 0.1% g = +2, v out = 2 v step 95 ns g = +2, v out = 8 v step 225 ns noise/harmonic performance distortion f c = 1 mhz, v out = 2 v p-p second harmonic r l = 500 ?82 dbc r l = 1 k ?85 dbc third harmonic r l = 500 ?70 dbc r l = 1 k ?81 dbc crosstalk, output-to-output f = 1 mhz, g = +2 ?86 db input voltage noise f = 100 khz 11 nv/hz input current noise f = 100 khz 0.7 fa/hz dc performance input offset voltage v cm = 0 v 1 2 mv t min ? t max 3.5 mv input offset voltage match 2.5 mv input offset voltage drift 4 27 v/c input bias current 1.5 11 pa t min ? t max 50 pa open-loop gain v out = 3 v 89 92 db input characteristics common-mode input impedance 1000||2.3 g||pf differential input impedance 1000||1.7 g||pf input common-mode voltage range fet input range ?5.0 to +2.2 v common-mode rejection ratio v cm = ?3 v to +1.5 v ?89 ?100 db output characteristics output voltage swing 4.75 4.95 v output short-circuit current 40 ma capacitive load drive 30% overshoot, g = +1, v out = 400 mv p-p 35 pf power supply operating range 5 24 v quiescent current per amplifier 3.3 3.5 ma power supply rejection ratio v s = 2 v ?90 ?100 db
ad8033/ad8034 rev. d | page 4 of 24 t a = 25c, v s = 5 v, r l = 1 k, gain = +2, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v out = 0.2 v p-p 70 80 mhz g = +2, v out = 0.2 v p-p 32 mhz g = +2, v out = 2 v p-p 21 mhz input overdrive recovery time ?3 v to +3 v input 180 ns output overdrive recovery time ?1.5 v to +1.5 v input, g = +2 200 ns slew rate (25% to 75%) g = +2, v out = 4 v step 55 70 v/s settling time to 0.1% g = +2, v out = 2 v step 100 ns noise/harmonic performance distortion f c = 1 mhz, v out = 2 v p-p second harmonic r l = 500 ?80 dbc r l = 1 k ?84 dbc third harmonic r l = 500 ?70 dbc r l = 1 k ?80 dbc crosstalk, output to output f = 1 mhz, g = +2 ?86 db input voltage noise f = 100 khz 11 nv/hz input current noise f = 100 khz 0.7 fa/hz dc performance input offset voltage v cm = 0 v 1 2 mv t min ? t max 3.5 mv input offset voltage match 2.5 mv input offset voltage drift 4 30 v/c input bias current 1 10 pa t min ? t max 50 pa open-loop gain v out = 0 v to 3 v 87 92 db input characteristics common-mode input impedance 1000||2.3 g||pf differential input impedance 1000||1.7 g||pf input common-mode voltage range fet input range 0 to 2.0 v common-mode rejection ratio v cm = 1.0 v to 2.5 v ?80 ?100 db output characteristics output voltage swing r l = 1 k 0.16 to 4.83 0.04 to 4.95 v output short-circuit current 30 ma capacitive load drive 30% overshoot, g = +1, v out = 400 mv p-p 25 pf power supply operating range 5 24 v quiescent current per amplifier 3.3 3.5 ma power supply rejection ratio v s = 1 v ?80 ?100 db
ad8033/ad8034 rev. d | page 5 of 24 t a = 25c, v s = 12 v, r l = 1 k, gain = +2, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v out = 0.2 v p-p 65 80 mhz g = +2, v out = 0.2 v p-p 30 mhz g = +2, v out = 2 v p-p 21 mhz input overdrive recovery time ?13 v to +13 v input 100 ns output overdrive recovery time ?6.5 v to +6.5 v input, g = +2 100 ns slew rate (25% to 75%) g = +2, v out = 4 v step 55 80 v/s settling time to 0.1% g = +2, v out = 2 v step 90 ns g = +2, v out = 10 v step 225 ns noise/harmonic performance distortion f c = 1 mhz, v out = 2 v p-p second harmonic r l = 500 ?80 dbc r l = 1 k ?82 dbc third harmonic r l = 500 ?70 dbc r l = 1 k ?82 dbc crosstalk, output to output f = 1 mhz, g = +2 ?86 db input voltage noise f = 100 khz 11 nv/hz input current noise f = 100 khz 0.7 fa/hz dc performance input offset voltage v cm = 0 v 1 2 mv t min ? t max 3.5 mv input offset voltage match 2.5 mv input offset voltage drift 4 24 v/c input bias current 2 12 pa t min ? t max 50 pa open-loop gain v out = 8 v 88 96 db input characteristics common-mode input impedance 1000||2.3 g||pf differential input impedance 1000||1.7 g||pf input common-mode voltage range fet input range ?12.0 to +9.0 v common-mode rejection ratio v cm = 5 v ?92 ?100 db output characteristics output voltage swing 11.52 11.84 v output short-circuit current 60 ma capacitive load drive 30% overshoot, g = +1 35 pf power supply operating range 5 24 v quiescent current per amplifier 3.3 3.5 ma power supply rejection ratio v s = 2 v ?85 ?100 db
ad8033/ad8034 rev. d | page 6 of 24 absolute maximum ratings table 4. parameter rating supply voltage 26.4 v power dissipation see figure 5 if the rms signal levels are indeterminate, consider the worst case, when v out = v s /4 for r l to midsupply p d = ( v s i s ) + ( v s /4) 2 / r l in single-supply operation with r l referenced to v s? , worst case is v out = v s /2. common-mode input voltage 26.4 v differential input voltage 1.4 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c ambient temperature (c) ?60 ?20 ?40 100 60 80 2.0 1.5 maximum power dissipation (w) 1.0 0.5 0 soic-8 sot-23-8 sc70-5 40 020 02924-005 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum safe power dissipation in the ad8033/ad8034 packages is limited by the associated rise in junction temperature (t j ) on the die. the plastic that encapsulates the die locally reaches the junction temperature. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8033/ ad8034. exceeding a junction temperature of 175c for an extended period can result in changes in silicon devices, potentially causing failure. figure 5. maximum power dissipation vs. ambient temperature for a 4-layer board airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the layout, grounding, and bypassing considerations section. figure 5 shows the maximum power dissipation in the package vs. the ambient temperature for the 8-lead soic (125c/w), 5-lead sc70 (210c/w), and 8-lead sot-23 (160c/w) packages on a jedec standard 4-layer board. ja values are approximations. the still-air thermal properties of the package and pcb ( ja ), ambient temperature (t a ), and the total power dissipated in the package (p d ) determine the junction temperature of the die. the junction temperature can be calculated as output short circuit shorting the output to ground or drawing excessive current for the ad8033/ad8034 will likely cause catastrophic failure. t j = t a + ( p d ja ) p d is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming the load (r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package esd caution p d = quiescent power + ( total drive power ? load power ) p d = [ v s i s ] + [( v s /2) ( v out / r l )] ? [ v out 2 / r l ] rms output voltages should be considered. if r l is referenced to ?v s , as in single-supply operation, the total drive power is v s i out .
ad8033/ad8034 rev. d | page 7 of 24 typical performance characteristics default conditions: v s = 5 v, c l = 5 pf, r l = 1 k, t a = 25c. 100 0.1 1 frequency (mhz) 21 18 ?9 15 12 9 6 3 0 ?3 ?6 24 gain (db) g = +5 1000 g = +1 v out = 200mv p-p g = +10 g = +2 g = ?1 10 02924-006 figure 6. small signal frequency response for various gains frequency (mhz) ?6 1 0 ?1 ?2 ?3 ?4 ?5 v s = +5v g = +1 v out = 200mv p-p gain (db) v s = 12v v s =5v 100 0.1 1 10 02924-007 figure 7. small signal frequency response for various supplies (see figure 44 ) frequency (mhz) 2 1 ?6 100 0.1 1 gain (db) 10 0 ?1 ?5 ?2 ?3 ?4 g = +1 v out = 2v p-p v s = 12v v s =5v v s = +5v 02924-008 figure 8. large signal frequency response for various supplies (see figure 44 ) frequency (mhz) 100 0.1 1 10 8 7 0 6 5 1 4 3 2 gain (db) v out = 1v p-p v out = 4v p-p v out = 2v p-p v out = 0.2v p-p g = +2 02924-009 figure 9. frequency response for various output amplitudes (see figure 45 ) 100 0.1 1 10 frequency (mhz) 8 7 0 6 5 1 4 3 2 gain (db) v s = +5v v s = 12v v s =5v g = +2 v out = 200mv p-p 02924-010 figure 10. small signal frequency response for various supplies (see figure 45 ) 100 0.1 1 10 frequency (mhz) 7 gain (db) 6 5 1 4 3 2 0 g = +2 v out = 2v p-p v s = 12v v s =5v v s = +5v 02924-011 figure 11. large signal frequenc y response for various supplies (see figure 45 )
ad8033/ad8034 rev. d | page 8 of 24 frequency (mhz) 100 0.1 11 0 8 6 4 ?4 2 0 ?2 ?6 gain (db) c l = 100pf c l = 100pf r snub = 25 ? c l = 33pf c l = 2pf v out = 200mv p-p g = +1 02924-012 figure 12. small signal frequency response for various c l (see figure 44 ) 100 0.1 11 0 9 8 0 7 6 2 5 4 3 1 gain (db) frequency (mhz) c f = 0pf c f = 1pf c f = 1.5pf c f = 2pf v out = 200mv p-p r f = 3k ? g = +2 02924-013 figure 13. small signal frequency response for various c f (see figure 45 ) frequency (hz) 0.1 impedance ( ? ) 100 10 1 g = +2 g = +1 v out = 200mv p-p 0.01 100 1k 10k 100k 1m 10m 100m 0 2924-014 figure 14. output impedance vs. frequency (see figure 47 ) 100 0.1 1 10 frequency (mhz) gain (db) 10 9 0 8 7 6 5 4 3 2 1 c l = 100pf c l = 51pf c l = 33pf c l = 2pf v out = 200mv p-p g = +2 02924-015 figure 15. small signal frequency response for various c l (see figure 45 ) frequency (mhz) 100 0.1 1 10 8 7 0 gain (db) 6 5 1 4 3 2 r l = 500 ? r l = 1k ? v out = 200mv p-p g = +2 02924-016 figure 16. small signal frequency response for various r l (see figure 45 ) frequency (hz) 100 1k 10k 100k 1m 10m 100m 100 80 ?20 gain (db) 40 20 0 60 180 150 0 phase (degrees) 90 60 30 120 gain phase v s = 12v 02924-017 figure 17. open-loop response
ad8033/ad8034 rev. d | page 9 of 24 frequency (mhz) ? 40 ?50 ?120 5 1 0.1 distortion (dbc) ?60 ?70 ?110 ?80 ?90 ?100 g = +2 hd2 r l = 500 ? hd2 r l = 1k ? hd3 r l = 1k ? hd3 r l = 500 ? 02924-018 figure 18. harmonic distortion vs. frequency for various loads (see figure 45 ) frequency (mhz) ? 40 ?50 ?120 5 0.1 1 distortion (dbc) ?60 ?70 ?110 ?80 ?90 ?100 g = +2 hd3 v s = 24v hd2 v s = 24v hd2 v s = 5v hd3 v s = 5v 02924-019 figure 19. harmonic distortion vs. frequency for various supply voltages (see figure 45 ) frequency (hz) 1000 10 m01 10 100 1k 10k 100k 1m 10m 100m noise (nv/ hz) 100 02924-020 figure 20. voltage noise vs. frequency frequency (mhz) ? 40 ?50 ?120 5 0.1 1 distortion (dbc) ?60 ?70 ?110 ?80 ?90 ?100 hd3 g = +2 hd2 g = +1 hd3 g = +1 hd2 g = +2 02924-021 figure 21. harmonic distortion vs. frequency for various gains frequency (mhz) ?40 ?50 ?120 5 0.1 1 distortion (dbc) ?60 ?70 ?110 ?80 ?90 ?100 hd3 v out = 20v p-p hd2 v out = 20v p-p hd3 v out = 10v p-p hd2 v out = 10v p-p hd3 v out = 2v p-p hd2 v out = 2v p-p ?30 ? 20 02924-022 g = +2 figure 22. harmonic distortion vs. frequency for various amplitudes (see figure 45 ), v s = 24 v capacitive load (pf) 80 0 percent overshoot (%) 70 40 30 20 10 60 50 10 30 50 70 90 110 v s = +5v positive side v s =5v positive side v s =5v negative side v s = +5v negative side 0 2924-023 g = +1 figure 23. percent overshoot vs. capacitive load (see figure 44 )
ad8033/ad8034 rev. d | page 10 of 24 g = +1 25mv/div 20ns/div 02924-024 figure 24. small signal transient response 5 v (see figure 44 ) 3v/div 320ns/div v out = 20v p-p v out = 8v p-p v out = 2v p-p 0 2924-025 g = +1 figure 25. large signal transient response (see figure 44 ) g = ?1 v in v out 1.5v/div 350ns/div 02924-026 figure 26. output ov erdrive recovery (see figure 46 ) g = +1 80mv/div 80ns/div 38pf 15pf 02924-027 figure 27. small signal transient response 5 v (see figure 44 ) 3v/div 320ns/div g = +2 v out = 2v p-p v out = 8v p-p v out = 20v p-p 02924-028 figure 28. large signal transient response (see figure 45 ) g = +1 v in v out 1.5v/div 350ns/div 02924-029 figure 29. input overdrive recovery (see figure 44 )
ad8033/ad8034 rev. d | page 11 of 24 2mv/div 1.5s/div v out ? 2v in v in = 1v t = 0 +0.1% ?0.1% 02924-030 figure 30. long-term settling time temperature (c) 85 20 25 30 35 40 45 50 60 65 70 8075 55 0 ?40 i b (pa) ?20 ?25 ?30 ?35 ?10 ?15 ?5 +i b ?i b 02924-031 figure 31. i b vs. temperature ?i b +i b ?i b +i b bjt input range fet input range common-mode voltage (v) ?4?6?8?10?12 ?2 02468 12 10 10 5 0 ?5 ?10 ?15 ?20 ?25 ?30 0 6 12 18 24 30 36 42 02924-032 i b ( a) i b ( p a) figure 32. i b vs. common-mode voltage range 2mv/div 20ns/div v in = 1v t = 0 +0.1% ?0.1% v out ? 2v in 02924-033 figure 33. 0.1% short-term settling time ?40 ?20 0 20406080 temperature (c) 7.0 6.4 5.9 quiescent supply current (ma) 6.9 6.7 6.2 6.0 6.6 6.8 6.5 6.3 6.1 02924-034 v s = +5v v s = 5v v s = 12v figure 34. quiescent supply current vs. temperature for various supply voltages 4.0 0.5 ?1.0 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 ?14 normalized offset (mv) 3.5 1.0 0 ?0.5 2.5 1.5 3.0 2.0 common-mode voltage (v) 02924-035 v s = +5v v s = 5v v s = 12v figure 35. input offset voltage vs. common-mode voltage
ad8033/ad8034 rev. d | page 12 of 24 frequency (mhz) cmrr (db) 0.1 1 10 100 0 2924-036 ? 20 ?30 ?40 ?50 ?60 ?70 ?80 figure 36. cmrr vs. frequency (see figure 50 ) i load (ma) 0 30 05 output saturation (v) 10 15 20 25 0.6 0.4 0.2 1.0 0.8 v cc ?v oh v ol ? v ee 02924-037 figure 37. output saturation voltage vs. load current frequency (mhz) psrr (db) 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?10 100 0.0001 0.001 0.01 0.1 1 10 +psrr ?psrr 02924-038 figure 38. psrr vs. frequency (see figure 49 and figure 51 ) output voltage (v) 12 ?10?8?6?4?2 246810 0 105 100 60 open-loop gain (db) 80 75 70 65 90 85 95 ?12 r l = 500 ? r l = 1k ? r l = 2k ? 0 2924-039 figure 39. open-loop gain vs. output voltage for various r l frequency (mhz) ? 40 ?70 ?100 0.1 crosstalk (db) 50 ?80 ?90 ?60 ?50 10 1 soic a/b soic b/a sot-23 b/a sot-23 a/b 0 2924-040 figure 40. crosstalk (see figure 52 ) v os (mv) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 frequency 120 90 60 30 180 150 02924-041 figure 41. initial offset
ad8033/ad8034 rev. d | page 13 of 24 1.2v/div 1s/div v in v out 0 2924-042 figure 42. g = +1 response, v s = 5 v 1.2v/div v in v out 1s/div 0 2924-043 figure 43. g = +2 response, v s = 5 v
ad8033/ad8034 rev. d | page 14 of 24 test circuits v in 49.9 ? ?v s +v s + 10nf ad8033/ad8034 10nf 1f 1f + c load r snub 49.9 ? 976 ? v out 02924-044 figure 44. g = +1 v in 49.9 ? ?v s +v s 1f 1f + 10nf ad8033/ad8034 10nf + c load r snub 49.9 ? 976 ? v out c f 1k ? r f 1k ? 499 ? 02924-045 figure 45. g = +2 49.9 ? 1k ? 1k ? 1f 1f 976 ? 499 ? +v s ?v s v in + 10nf ad8033/ad8034 10nf + v out 02924-046 figure 46. g = ?1 1 f 1f +v s ?v s + 10nf ad8033/ad8034 10nf v sine 0.2v p-p + + ? 02924-047 figure 47. output impedance, g = +1 1k ? 1k ? 1f 1f +v s ?v s + 10nf ad8033/ad8034 10nf + v sine 0.2v p-p + ? 02924-048 figure 48. output impedance, g = +2
ad8033/ad8034 rev. d | page 15 of 24 +v s 49.9 ? 1f + 10nf ad8033/ad8034 v out + ? ?v s ?v s ac 1v p-p 02924-051 figure 49. negative psrr 49.9 ? +v s v in ?v s 1f 1f + 10nf ad8033/ad8034 10nf + 976 ? v out 1k ? 1k ? 49.9 ? 1k ? 1k ? 02924-050 figure 50. cmrr +v s + ? +v s ac 1v p- p 49.9 ? v out ?v s ad8033/ad8034 10nf 1f + 02924-049 figure 51. positive psrr ?v s +v s ?v s +v s a + ? 499 ? 1k ? 1k ? 1k ? to port 2 b + ? 1k ? 1k ? 1k ? 499 ? to port 1 50 ? + ? v in 02924-052 figure 52. crosstalk
ad8033/ad8034 rev. d | page 16 of 24 theory of operation the incorporation of jfet devices into the analog devices high voltage xfcb process has enabled the ability to design the ad8033/ad8034. the ad8033/ad8034 are voltage feedback rail-to-rail output amplifiers with fet inputs and a bipolar- enhanced common-mode input range. the use of jfet devices in high speed amplifiers extends the application space into both the low input bias current and low distortion, high bandwidth areas. using n-channel jfets and a folded cascade input topology, the common-mode input level operates from 0.2 v below the negative rail to within 3.0 v of the positive rail. cascading of the input stage ensures low input bias current over the entire common-mode range as well as cmrr and psrr specifications that are above 90 db. additionally, long-term settling issues that normally occur with high supply voltages are minimized as a result of the cascading. output stage drive and capacitive load drive the common emitter output stage adds rail-to-rail output performance and is compensated to drive 35 pf (30% overshoot at g = +1). additional capacitance can be driven if a small snub resistor is put in series with the capacitive load, effectively decoupling the load from the output stage, as shown in figure 12 . the output stage can source and sink 20 ma of current within 500 mv of the supply rails and 1 ma within 100 mv of the supply rails. input overdrive an additional feature of the ad8033/ad8034 is a bipolar input pair that adds rail-to-rail common-mode input performance specifically for applications that cannot tolerate phase inversion problems. under normal common-mode operation, the bipolar input pair is kept reversed, maintaining i b at less than 1 pa. when the input common-mode operation comes within 3.0 v of the positive supply rail, i1 turns off and i4 turns on, supplying tail current to the bipolar pair q25 and q27. with this configuration, the inputs can be driven beyond the positive supply rail without any phase inversion (see figure 53 ). as a result of entering the bipolar mode of operation, an offset and input bias current shift occurs (see figure 32 and figure 35 ). after re-entering the jfet common-mode range, the amplifier recovers in approximately 100 ns (refer to figure 29 for input overload behavior). above and below the supply rails, esd protection diodes activate, resulting in an exponentially increasing input bias current. if the inputs are driven well beyond the rails, series input resistance should be included to limit the input bias current to <10 ma. input impedance the input capacitance of the ad8033/ad8034 forms a pole with the feedback network, resulting in peaking and ringing in the overall response. the equivalent impedance of the feedback network should be kept small enough to ensure that the parasitic pole falls well beyond the ?3 db bandwidth of the gain configuration being used. if larger impedance values are desired, the amplifier can be compensated by placing a small capacitor in parallel with the feedback resistor. figure 13 shows the improvement in frequency response by including a small feedback capacitor with high feedback resistance values. thermal considerations because the ad8034 operates at up to 12 v supplies in the small 8-lead sot-23 package (160c/w), power dissipation can easily exceed package limitations, resulting in permanent shifts in device characteristics and even failure. likewise, high supply voltages can cause an increase in junction temperature even with light loads, resulting in an input bias current and offset drift penalty. the input bias current doubles for every 10c shown in figure 31 . refer to the maximum power dissipation section for an estimation of die temperature based on load and supply voltage.
ad8033/ad8034 rev. d | page 17 of 24 v th + v s r2 q6 ?in j1 d4 q25 q7 i2 q27 r3 r14 q9 ?v s j2 +in r7 q29 q4 q13 v cc q11 i3 q28 r8 q1 q14 v2 v4 + + ? ? v out d5 i1 i4 02924-053 figure 53. simplified ad8033/ad8034 input stage
ad8033/ad8034 rev. d | page 18 of 24 layout, grounding, and by passing considerations bypassing power supply pins are actually inputs, and care must be taken so that a noise-free stable dc voltage is applied. the purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering a majority of the noise. decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. the chip capacitors, 0.01 f or 0.001 f (x7r or npo), are critical and should be placed as close as possible to the amplifier package. larger chip capacitors, such as the 0.1 f capacitor, can be shared among a few closely spaced active components in the same signal path. the 10 f tantalum capacitor is less critical for high frequency bypassing, and in most cases, only one per board is needed at the supply inputs. grounding a ground plane layer is important in densely packed pcbs to spread the current, thereby minimizing parasitic inductances. however, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. the length of the current path is directly proportional to the magnitude of the parasitic inductances and, thus, the high frequency impedance of the path. high speed currents in an inductive ground return create unwanted voltage noise. the length of the high frequency bypass capacitor leads is most critical. a parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. place the ground leads of the bypass capacitors at the same physical location. because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. for the larger value capacitors that are intended to be effective at lower frequencies, the current return path distance is less critical. leakage currents poor pcb layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias currents of the ad8033/ad8034. any voltage differential between the inputs and nearby runs set up leakage currents through the pcb insulator, for example, 1 v/100 g = 10 pa. similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). to significantly reduce leakages, put a guard ring (shield) around the inputs and input leads that is driven to the same voltage potential as the inputs. this way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. for the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above, and below using a multilayer board. another effect that can cause leakage currents is the charge absorption of the insulator material itself. minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. in addition, low absorption materials such as teflon? or ceramic may be necessary in some instances. input capacitance along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. a few pf of capacitance reduces the input impedance at high frequencies, in turn it increases the gain of the amplifier and can cause peaking of the overall frequency response or even oscillations if severe enough. it is recommended that the external passive components that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. the ground and power planes must be kept at a distance of at least 0.05 mm from the input pins on all layers of the board.
ad8033/ad8034 rev. d | page 19 of 24 applications information high speed peak detector the low input bias current and high bandwidth of the ad8033/ ad8034 make the parts ideal for a fast settling, low leakage peak detector. the classic fast-low leakage topology with a diode in the output is limited to ~1.4 v p-p maximum in the case of the ad8033/ad8034 because of the protection diodes across the inputs, as shown in figure 54 . ad8033/ ad8034 v in ~1.4v p-p max v out 02924-054 figure 54. high speed peak det ector with limited input range using the ad8033/ad8034, a unity gain peak detector can be constructed that captures a 300 ns pulse while still taking advantage of the low input bias current and wide common- mode input range of the ad8033/ad8034, as shown in figure 55 . using two amplifiers, the difference between the peak and the current input level is forced across r2 instead of either amplifiers input pins. in the event of a rising pulse, the first amplifier compensates for the drop across d2 and d3, forcing the voltage at node 3 equal to node 1. d1 is off and the voltage drop across r2 is zero. capacitor c3 speeds up the loop by providing the charge required by the input capacitance of the first amplifier, helping to maintain a minimal voltage drop across r2 in the sampling mode. a negative going edge results in d2 and d3 turning off and d1 turning on, closing the loop around the first amplifier and forcing v out ? v in across r2. r4 makes the voltage across d2 zero, minimizing leakage current and kickback from d3 from affecting the voltage across c2. the rate of the incoming edge must be limited so that the output of the first amplifier does not overshoot the peak value of v in before the output of the second amplifier can provide negative feedback at the summing junction of the first amplifier. this is accomplished with the combination of r1 and c1, which allows the voltage at node 1 to settle to 0.1% of v in in 270 ns. the selection of c2 and r3 is made by considering droop rate, settling time, and kickback. r3 prevents overshoot from occurring at node 3. the time constants of r1, c1 and r3, c2 are roughly equal to achieve the best performance. slower time constants can be selected by increasing c2 to minimize droop rate and kickback at the cost of increased settling time. r1 and c1 should also be increased to match, reducing the incoming pulses effect on kickback. ad8034 1/2 c3 10pf r2 1k ? r1 1k ? ad8034 1/2 ?v s +v s c1 39pf/ 120pf ls4148 v in r5 49.9 ? d1 4.7pf c4 r4 6k? d3 ls4148 ?v s +v s ls4148 r3 200 ? c2 180pf/ 560pf v out d2 0 2924-056 figure 55. high speed, unity gain peak detector using ad8034
ad8033/ad8034 rev. d | page 20 of 24 1v/div 100ns/div 02924-055 output input 2 figure 56. peak detector response 4 v, 300 ns pulse figure 56 shows the peak detector in figure 55 capturing a 300 ns, 4 v pulse with 10 mv of kickback and a droop rate of 5 v/s. for larger peak-to-peak pulses, increase the time constants of r1, c1 and r3, c3 to reduce overshoot. the best droop rate occurs by isolating parasitic resistances from node 3, which can be accomplished using a guard band connected to the output of the second amplifier that surrounds its summing junction (node 3). increasing both time constants by a factor of 3 permits a larger peak pulse to be captured and increases the output accuracy. 1v/div 200ns/div 02924-057 output input 2 figure 57. peak detector response 5 v, 1 s pulse figure 57 shows a 5 v peak pulse being captured in 1 s with less than 1 mv of kickback. with this selection of time constants, up to a 20 v peak pulse can be captured with no overshoot. active filters the response of an active filter varies greatly depending on the performance of the active device. open-loop bandwidth and gain, along with the order of the filter, determines the stop-band attenuation as well as the maximum cutoff frequency, while input capacitance can set a limit on which passive components are used. topologies for active filters are varied, and some are more dependent on the performance of the active device than others are. the sallen-key topology is the least dependent on the active device, requiring that the bandwidth be flat to beyond the stop- band frequency because it is used simply as a gain block. in the case of high q filter stages, the peaking must not exceed the open- loop bandwidth and the linear input range of the amplifier. using an ad8033/ad8034, a 4-pole cascaded sallen-key filter can be constructed with f c = 1 mhz and over 80 db of stop-band attenuation, as shown in figure 58 . ?v s +v s c2 10pf ?v s +v s v in r1 4.22k ? ad8034 1/2 ad8034 1/2 r2 6.49k ? r5 49.9 ? c1 27pf c3 33pf r4 4.99k ? r3 4.99k ? c4 82pf v out 02924-058 figure 58. 4-pole cascade sallen-key filter component values are selected using a normalized cascaded, 2-stage butterworth filter table and sallen-key 2-pole active filter equations. the overall frequency response is shown in figure 59 . 10m 1m 10k frequency (hz) ?100 ref level (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100k 0 2924-059 figure 59. 4-pole cascade sallen-key filter response
ad8033/ad8034 rev. d | page 21 of 24 when selecting components, the common-mode input capacitance must be taken into consideration. filter cutoff frequencies can be increased beyond 1 mhz using the ad8033/ad8034 but limited open-loop gain and input impedance begin to interfere with the higher q stages. this can cause early roll-off of the overall response. additionally, the stop-band attenuation decreases with decreasing open-loop gain. keeping these limitations in mind, a 2-pole sallen-key butterworth filter with f c = 4 mhz can be constructed that has a relatively low q of 0.707 while still maintaining 15 db of attenuation an octave above f c and 35 db of stop-band attenuation. the filter and response are shown in figure 60 and figure 61 , respectively. ?v s +v s v in r1 2.49k ? c3 22pf v out ad8033 r2 2.49k ? r5 49.9 ? c1 10pf 02924-060 figure 60. 2-pole butte rworth active filter 100m 100k 1m frequency (hz) ?45 gain (db) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 2924-061 10m figure 61. 2-pole butterworth active filter response wideband photodiode preamp figure 62 shows an i/v converter with an electrical model of a photodiode. the basic transfer function is ff f photo out rsc r i v + = 1 where i photo is the output current of the photodiode, and the parallel combination of r f and c f sets the signal bandwidth. c s r sh = 10 11 ? v b i photo 02924-062 r f c f v out c m r f c m c d c f + c s figure 62. wideband photodiode preamp the stable bandwidth attainable with this preamp is a function of r f , the gain bandwidth product of the amplifier, and the total capacitance at the summing junction of the amplifier, including c s and the amplifier input capacitance. r f and the total capacitance produce a pole in the loop transmission of the amplifier that can result in peaking and instability. adding c f creates a zero in the loop transmission that compensates for the effect of the pole and reduces the signal bandwidth. it can be shown that the signal bandwidth resulting in a 45phase margin (f (45) ) is defined by the expression s f cr cr f f = 2 )45( where: f cr is the amplifier crossover frequency. r f is the feedback resistor. c s is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). the value of c f that produces f (45) is cr f s f fr c c = 2 the frequency response in this case shows about 2 db of peaking and 15% overshoot. doubling c f and cutting the bandwidth in half results in a flat frequency response, with about 5% transient overshoot.
ad8033/ad8034 rev. d | page 22 of 24 02924-063 frequency (hz) voltage noise (nv/ hz) 2 r f c f 2 r f (c f + c s + c m + 2c d ) (c s + c m + 2c d + c f )/c f rf noise ven (c f + c s + c m + 2c d )/c f f 3 f 2 f 3 = ven f 1 f 2 = f 1 = 1 1 f cr noise due to amplifier the output noise over frequency of the preamp is shown in figure 63 . the pole in the loop transmission translates to a zero in the noise gain of the amplifier, leading to an amplification of the input voltage noise over frequency. the loop transmission zero introduced by c f limits the amplification. the bandwidth of the noise gain extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects that add to the output noise. integrating the square of the output voltage noise spectral density over frequency and then taking the square root results in the total rms output noise of the preamp. figure 63. photodiode voltage noise contributions
ad8033/ad8034 rev. d | page 23 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 64. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-203-aa 0.30 0.15 0 . 1 0 m a x 1.00 0.90 0.70 0.46 0.36 0.26 seating plane 0.22 0.08 1.10 0.80 4 5 123 pin 1 0.65 bsc 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.10 coplanarity 0.40 0.10 figure 65. 5-lead thin shrink small outline transistor package [sc70] (ks-5) dimensions shown in millimeters 13 56 2 8 4 7 2.90 bsc 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc pin 1 indicator compliant to jedec standards mo-178-b a figure 66. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters
ad8033/ad8034 rev. d | page 24 of 24 ordering guide model temperature range package description package option branding ad8033ar C40c to +85c 8-lead soic_n r-8 ad8033ar-reel C40c to +85c 8-lead soic_n r-8 ad8033ar-reel7 C40c to +85c 8-lead soic_n r-8 ad8033arz 1 C40c to +85c 8-lead soic_n r-8 ad8033arz-reel 1 C40c to +85c 8-lead soic_n r-8 ad8033arz-reel7 1 C40c to +85c 8-lead soic_n r-8 ad8033aks-r2 C40c to +85c 5-lead sc70 ks-5 h3b ad8033aks-reel C40c to +85c 5-lead sc70 ks-5 h3b ad8033aks-reel7 C40c to +85c 5-lead sc70 ks-5 h3b ad8033aksz-r2 1 C40c to +85c 5-lead sc70 ks-5 h3c ad8033aksz-reel 1 C40c to +85c 5-lead sc70 ks-5 h3c ad8033aksz-reel7 1 C40c to +85c 5-lead sc70 ks-5 h3c ad8034ar C40c to +85c 8-lead soic_n r-8 ad8034ar-reel7 C40c to +85c 8-lead soic_n r-8 ad8034ar-reel C40c to +85c 8-lead soic_n r-8 ad8034arz 1 C40c to +85c 8-lead soic_n r-8 ad8034arz-reel 1 C40c to +85c 8-lead soic_n r-8 ad8034arz-reel7 1 C40c to +85c 8-lead soic_n r-8 ad8034art-r2 C40c to +85c 8-lead sot-23 rj-8 hza ad8034art-reel C40c to +85c 8-lead sot-23 rj-8 hza ad8034art-reel7 C40c to +85c 8-lead sot-23 rj-8 hza ad8034artz-r2 1 C40c to +85c 8-lead sot-23 rj-8 hza# AD8034ARTZ-REEL 1 C40c to +85c 8-lead sot-23 rj-8 hza# AD8034ARTZ-REEL7 1 C40c to +85c 8-lead sot-23 rj-8 hza# ad8034chips die 1 z = rohs compliant part, # denotes rohs comp liant product may be top or bottom marked. ?2002C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02924-0-9/08(d)

▲Up To Search▲

Price & Availability of AD8034ARTZ-REEL

	To Download AD8034ARTZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .